? semiconductor components industries, llc, 2001 january, 2001 rev. 4 1 publication order number: mc100lvel38/d mc100lvel38 3.3vecl 2, 4/6 clock generation chip the mc100lvel38 is a low skew 2, 4/6 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the device can be driven by either a differential or single-ended input signal. the common enable (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. the phase_out output will go high for one clock cycle whenever the 2 and the 4/6 outputs are both transitioning from a low to a high. this output allows for clock synchronization within the system. upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple lvel38s, the master reset (mr) input must be asserted to ensure synchronization. for systems which only use one lvel38, the mr pin need not be exercised as the internal divider design ensures synchronization between the 2 and the 4/6 outputs of a single device. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? 50 ps maximum output-to-output skew ? synchronous enable/disable ? master reset for synchronization ? esd protection: >2 kv hbm ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 388 devices http://onsemi.com marking diagram 1 20 a = assembly location wl = wafer lot yy = year ww = work week so20 dw suffix case 751d 100lvel38 awlyyww 1 20 device package shipping ordering information mc100lvel38dw soic20 38 units/rail mc100lvel38dwr2 soic20 1000 units/reel
mc100lvel38 http://onsemi.com 2 clk pinout: 20-lead soic (top view) clk mr v cc 17 18 16 15 14 13 12 4 3 5678 9 q0 11 10 q1 q1 q2 q2 q3 q3 v ee en 19 20 2 1 v cc q0 phase_out phase_out div_sel v bb v cc divsel q 2 , q 3 outputs l divide by 4 h divide by 6 pin function clk, clk ecl diff clock inputs q 0 , q 1; q 0 , q 1 ecl diff 2 outputs q 2 , q 3; q 2 , q 3 ecl diff 4/6 outputs en ecl sync enable input mr ecl master reset input divsel ecl frequency select input phase_out, phase_out ecl phase sync diff. signal output v bb reference voltage output v cc positive supply v ee negative supply pin description clk z zz x en l h x mr l l h function divide hold q 03 reset q 03 function table z = low-to-high transition zz = high-to-low transition x = don't care warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. phase out logic clk clk en mr divsel 2 q0 q0 q1 q1 4/6 q2 q2 q3 q3 phase_out phase _out logic diagram r r r r v bb
mc100lvel38 http://onsemi.com 3 clk q ( 2) q ( 4) q ( 6) phase_out ( 4) phase_out ( 6) figure 1. timing diagrams maximum ratings (note 1.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6o0 6 to 0 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 soic 20 soic 90 60 c/w c/w q jc thermal resistance (junction to case) std bd 20 soic 30 to 35 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100lvel38 http://onsemi.com 4 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 50 60 50 60 54 65 ma v oh output high voltage (note 2.) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2.) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 3.) 1.65 2.75 1.65 2.75 1.65 2.75 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1.0 v. lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 50 60 50 60 54 65 ma v oh output high voltage (note 2.) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2.) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3.) 1.65 0.55 1.65 0.55 1.65 0.55 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1.0 v.
mc100lvel38 http://onsemi.com 5 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay clk to q (diff) to output clk to q (s.e.) clk to phase_out (diff) clk to phase_out (s.e.) mr to.q 760 710 800 750 510 960 1010 1000 1050 810 800 750 840 790 540 1000 1050 1040 1090 840 850 800 890 840 570 1050 1100 1090 1140 870 ps t skew within-device skew (note 2.) q 0 q 3 all 50 75 50 75 50 75 ps part-to-part q 0 q 3 (diff) all 200 240 200 240 200 240 t jitter cycletocycle jitter tbd tbd tbd ps t s setup time en to clk divsel to clk 150 150 150 ps t h hold time clk to en clk to div_sel 150 200 150 200 150 200 ps v pp input swing (note 3.) clk 250 1000 250 1000 250 1000 mv t rr reset recovery time 100 100 100 ps t pw minimum pulse width clk mr 800 700 800 700 800 700 ps t r , t f output rise/fall times q (20% 80%) 280 550 280 550 280 550 ps 1. v ee can vary 0.3 v. 2. skew is measured between outputs under identical transitions. 3. v pp (min) is minimum input swing for which ac parameters are guaranteed. the device will function reliably with differential inputs down to 100 mv. v tt = v cc 2.0 v figure 2. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt
mc100lvel38 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lvel38 http://onsemi.com 7 package dimensions soic20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100lvel38 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100lvel38/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
|
